1. Field of the Invention
This invention relates to transconductance stages designed to produce a differential output current in response to a differential input voltage.
2. Description of the Related Art
Transconductance stages are commonly employed to convert a differential voltage input signal to a differential current output signal with amplification for application to a downstream stage of an overall circuit. Transconductance stages are applicable to circuits such as operational amplifiers, digital-to-analog converters, analog-to-digital converters, power amplifiers, buffers, comparators and instrumentation amplifiers.
The two common forms of transconductance stages use either bipolar transistors or junction field effect transistors (JFETs). The selection of one type or the other involves a trade-off between the particular advantages of each.
A conventional transconductance stage employing bipolar input transistors is shown in FIG. 1. A differential input voltage signal is applied across a pair of input terminals IN1 and IN2, which are connected respectively to the bases of input bipolar transistors Q1 and Q2. The transistors are illustrated as pnp devices, but the circuit could be re-configured with reverse polarities for npn transistors.
A current source I1 is biased by a positive voltage bus V+to supply current to the common emitter connection of Q1 and Q2. The collectors of Q1 and Q2 are connected through respective resistors R1 and R2 to a negative voltage bus V-. A differential current output is taken from the collectors of Q1 and Q2 and delivered to the next stage, illustrated as operational amplifier 2, in the overall circuit. The input transconductance stage may be designed to also provide a voltage gain if required by the second stage, but voltage gain is not required in all cases. The transconductance stage generally drives some form of load capacitance such as a phase compensation circuit.
The output differential current (the difference between the two currents supplied to the second stage 2) is the product of the input voltage differential times the transconductance g.sub.m of the transconductance stage. The bipolar stage of FIG. 1 is characterized by a high g.sub.m, which results in a good high frequency response with an accompanying wide bandwidth, and a low level of background noise. However, bipolar input stages saturate at a relatively low input voltage level of about 100 mV, resulting in a limited output current and degradation of slew rate for large signal inputs.
A typical JFET transconductance input stage is shown in FIG. 2. This circuit is essentially similar to that of FIG. 1, except that bipolar transistors Q1 and Q2 have been replaced by JFETs J1 and J2, with the input voltage signals applied to their gates. The JFET circuit will not saturate up to input voltages of about 1 V, and therefore exhibits a higher slew rate for large signal inputs than the bipolar circuit. On the other hand, the JFET stage has a lower g.sub.m than the bipolar stage, resulting in a corresponding reduction in bandwidth and increase in background noise level.